IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 9, SEPTEMBER 2014
Active Mode Subclock Power Gating
Jatin N. Mistry, Member, IEEE, James Myers, Bashir M. Al-Hashimi, Fellow, IEEE,
David Flynn, Senior Member, IEEE, John Biggs, Member, IEEE, and Geoff V. Merrett, Member, IEEE
Abstract— This paper presents a technique, called subclock
power gating, for reducing leakage power during the active
mode in low performance, energy-constrained applications. The
proposed technique achieves power reduction through two mechanisms: 1) power gating the combinational logic within the clock
period (subclock) and 2) reducing the virtual supply to less
than ...view middle of the document...
when the digital circuit is doing useful work. A number of
techniques have been proposed for reducing active leakage
power dissipation. These include dual threshold logic 
which uses high threshold voltage logic gates on noncritical
timing paths and adaptive body biasing , which raises or
lowers the threshold voltage of transistors for active power
management. The effectiveness of power gating to reduce
leakage power has also been demonstrated during active mode.
A ﬁner granularity power gating has been proposed in ,
which involves disabling executional units during active mode.
Similarly, a method of power gating part of a multiplier
depending on the data width during run-time was proposed
in . Recent work has demonstrated the use of power gating
on a granularity akin to clock gating. The use of the clock
Manuscript received December 14, 2012; revised June 26, 2013; accepted
August 20, 2013. Date of publication September 20, 2013; date of current
version August 21, 2014.
J. Mistry, J. Myers, D. Flynn, and J. Biggs are with ARM Ltd., Cambridge
CB1 9NJ, U.K. (e-mail: firstname.lastname@example.org; email@example.com;
B. M. Al-Hashimi and G. V. Merrett are with the School of Electronics
and Computer Science, University of Southampton, Southampton SO17 1BJ,
U.K. (e-mail: firstname.lastname@example.org; email@example.com).
Color versions of one or more of the ﬁgures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identiﬁer 10.1109/TVLSI.2013.2280886
enables signal to power gate an integer execution core was
shown in . On the other hand, the use of the clock enable
signals to power gate the fan-in logic of the clock-gated
registers was shown in . All these methods attempt to reduce
power with minimal impact on maximum clock frequency.
In some current and emerging applications such as wireless
sensor nodes and biomedical sensor applications, performance
is not critical (10–100s kHz) whereas power and energy is the
primary design goal (10–100s µW). Recent work has demonstrated the use of aggressive voltage scaling, known as subthreshold operation, to improve energy efﬁciency with impact
on performance . This technique, however, has two critical barriers to its adoption: process-related variability, which
affects circuit reliability, and the complex design ﬂow required
for implementation . Instead, to avoid this complexity,
active power reduction is primarily targeted through choice
of a low super threshold voltage and low clock frequency
in some applications. Examples of this principal are reported
in , which utilizes a Texas Instruments MSP430  at
1.8 V and uses its 32 kHz mode of operation for device
control consuming 300 µW. Similarly, an ASIC for wireless
sensor nodes, which operates at 1 V and 10–100 kHz, is
reported in  and an ASIC for wireless monitoring of
an Electrocardiography (ECG) signal that...